1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having a circuit consisted of a thin film transistor (hereinafter, abbreviated as TFT), and particularly, relates to a method of forming a mask in an exposure step and a method of etching using the relevant mask.
2. Description of Related Art
In recent years, an active matrix type liquid crystal display utilizing a TFT has attracted a great deal of attention. An active matrix type liquid crystal display is provided with a TFT as a switching element at each pixel.
In general, in a TFT, a channel formation region is formed with an amorphous silicon or a polycrystalline silicon. Particularly, since a TFT using a polycrystalline silicon which is fabricated particularly at a temperature of being equal to 600xc2x0 C. or less (referred to as low temperature process) (hereinafter, referred to as polycrystalline silicon TFT) is capable of being formed on a glass substrate, it becomes possible to lower the cost of a semiconductor device and make the area of it larger. Moreover, in the case of a polycrystalline silicon, since the mobility of it is large, it is possible to realize a liquid crystal display in which a pixel section and a driver are integrally formed on a glass substrate.
However, if a polycrystalline silicon TFT is continuously driven, the mobility may be changed, ON-state current (current flowing in the case where a TFT is in an ON-state) may be increased, and OFF-state current (current flowing in the case where a TFT is in an OFF-state) may be increased. It is considered that this may be caused by the deterioration due to a hot carrier occurred by a high electric field nearby a drain.
In order to relax the high electric field nearby the drain and suppress the hot carrier, in the case of a MOS transistor employing the design rule of 1.5 xcexcm or less in a gate line width, it is useful to utilize a LDD (abbreviated from Lightly Doped Drain).
For example in the case of a NMOS (n-type MOSFET) transistor, a LDD structure can be formed by providing a low concentration n-type region (nxe2x88x92 region) at the edge portion of the drain utilizing a side wall of the gate side wall. The electric field nearby the drain can be relaxed by employing a LDD structure in which a concentration of impurity of drain junction is made hold a gradient.
In a LDD structure, a drain breakdown voltage can be enhanced comparing to a single drain structure. However, since the resistance of the nxe2x88x92 region is large, there is a difficulty that a drain current is reduced. Moreover, since a high electric field exists immediately under the side wall, where the ionization of collision becomes the maximum, and a hot electron is injected into a side wall, the nxe2x88x92 region is depleted, and further the resistance is increased, and finally a TFT is made deteriorated.
Particularly, the above-described problem becomes significant according to the reduction of the length of a channel. In order to overcome this problem in the case of a MOS transistor whose design rule is 0.5 xcexcm or less, a Gate Overlap LDD structure which forms the nxe2x88x92 region by overlapping at the edge portion of a gate electrode is useful.
Then, the employment of a Gate Overlap LDD structure has been considered in order to relax the high electric field nearby the drain not only in a MOS transistor but also in a polycrystalline silicon TFT. As for a polycrystalline silicon TFT having a Gate Overlap LDD structure, in a polycrystalline silicon layer, a channel formation region, a source region and a drain region which are high concentration regions (n+ region), and a low concentration region (nxe2x88x92 region) which has been provided between the channel formation region and the source and drain regions and which is overlapped with a gate electrode are formed.
As a method of fabricating these structures, there have been reports described in the patent document 1, the patent document 2 and the like.
Patent document 1: Japanese Unexamined Patent Publication No. 2000-349297 gazette, and
Patent document 2: Japanese Unexamined Patent Publication No. H07-202210 gazette.
In the step of fabricating a TFT having a Gate Overlap LDD structure, in order to form a low concentration region (nxe2x88x92 region) which is overlapped with a gate electrode, it is necessary to perform the step of adding an impurity element before the formation of a gate electrode, or to add an impurity element so that the impurity element penetrates through the gate electrode.
In the case of the former method, it is necessary to utilize a mask for adding an impurity element and a mask for forming a gate electrode in the separate exposure steps. Therefore, the gate electrode and the nxe2x88x92 region cannot be formed in a self-aligned process, the number of masks cannot be suppressed.
On the other hand, in the case of the latter method, it is necessary to add an impurity element only to the nxe2x88x92 region after a strategy has been taken so that the impurity is not added to the channel region. Therefore, in the case where the addition of an impurity to the channel region is prevented by utilizing the gate electrode itself as a mask, it is necessary to contrive the shape of the gate electrode by thickening the gate electrode only on the channel region and so forth.
However, in order to prevent the addition of the impurity to the channel region by contriving the shape of the gate electrode, in general, the exposure step is necessarily required multiple times. Therefore, it is difficult to precisely control the shape of the gate electrode by a mask shift in the respective exposure steps, the nxe2x88x92 region cannot be formed in a self-aligned process. Moreover, the number of reticles to be used is increased, and the fabrication steps become complex.
Moreover, usually, the larger the size of the resist mask becomes, the more the restraint of the conditions concerning with the patterning such as depth of focus, resist film thickness uniformity and the like becomes moderate, therefore, the process margin of the patterning step becomes larger. However, in the conventional methods, since the size and the shape of the resist mask are almost the same with the design sizes of the pattern, the more the miniaturization is progressed, the more the process margin of the patterning process is reduced, and it becomes difficult to fabricate a TFT.
For example, in the patent document 1, a method has been disclosed, in which a gate electrode having a two-layer structure is used, the step of etching a gate electrode is provided twice, and what is called a hut shape gate in which the first layer of the gate electrode is longer than the second layer in a channel length direction, is formed. Moreover, in Japanese Unexamined Patent Publication No. H07-202210 gazette, an example of a method of forming a hut shape gate in a self-aligned process has been described. A method has been described, in which the first layer of a gate electrode comprising titanium or a titanium nitride film and the second layer of a gate electrode comprising aluminum or an aluminum alloy film are formed by a DC (Direct Current) sputtering method. Subsequently, after both the first and second layers of the gate electrode have been etched by an etching treatment, only the gate electrode of the second layer is set back and processed by a side etching.
Moreover, in the technology disclosed in the patent document 2, since aluminum is used for the second layer of the gate electrode, which is different from the gate electrode such as a polycrystalline silicon having an excellent heat resistance, in the heat treatment at a high temperature, the failure due to the aluminum spike and the migration occur, there is a problem that the control of temperature is very difficult. Therefore, it is necessary to perform the activation of the impurity at a temperature at which aluminum is not denatured. However, the activation treatment after the ion injection or the ion doping is performed at a temperature between 550-800xc2x0 C., therefore, it is difficult to completely perform the activation treatment of the impurity at a temperature lower than that. Except for these, there are problems that in the case where aluminum is used, the surface becomes in a wavy state because aluminum is re-crystallized at a low temperature, or since it is a soft metal, it tends to be subjected to the mechanical damage.
Due to the reasons described above, it has been difficult to fabricate a TFT having a Gate Overlap LDD structure within the design rule in which the channel length is made in the range from about 1 to about 2 xcexcm, the overlapping width of the LDD region with an gate electrode is made 0.5 xcexcm or less. Specifically, a method of fabricating a conventional Gate Overlap LDD structure has problems as the followings:
1) The method requires the photolithography step multiple times,
2) the more the miniaturization is progressed, the more the process margin of the patterning step is reduced, and the fabrication becomes difficult, and
3) as the invention described in Japanese Unexamined Patent Publication No. H07-202210, in a method of fabricating a hut shape gate electrode by performing the patterning once, it has such a variety of problems that it is not preferable that the second layer of the gate electrode is limited to an aluminum film or an aluminum alloy film and the like.
An object of the present invention is to solve the above-described problems. Concretely, an object of the present invention is to suppress the number of photolithography steps and to provide a technology capable of fabricating the relevant TFT with an excellent precision even if the design rule is miniaturized in a step of fabricating a TFT having a Gate Overlap LDD structure.
It will be described of means for solving the problems such as the necessity of the photolithography step performing multiple times accompanying with the formation of a Gate Overlap LDD structure in a self-aligned process, the diminishing of a margin of the patterning and the reducing number of options for gate materials and the like in a process in which the miniaturization has been progressed.
It should be noted that in the present specification, the following definition is provided in order to clearly describe methods of fabricating a Gate Overlap LDD structure and the like. The region that is not overlapped with the gate electrode out of the LDD region is defined as a xe2x80x9cLoff regionxe2x80x9d, and the region that is overlapped with the gate electrode out of the LDD region is defined as a xe2x80x9cLov regionxe2x80x9d. The length of the Loff region is defined as xe2x80x9cLoffxe2x80x9d, and the length of the Lov region is defined as xe2x80x9cLovxe2x80x9d and the length of the channel region is defined as xe2x80x9cLixe2x80x9d. Moreover, in the present specification, as far as it is not clearly described, Lov regions whose lengths are equal to xe2x80x9cLovxe2x80x9d are defined to exist on both sides of the channel region, and then, the total length of the channel region and the Lov regions, specifically, the width xe2x80x9cLxe2x80x2xe2x80x9d of the entire gate electrode on the active layer is defined by the equation of xe2x80x9cLxe2x80x2=Li+Lovxc3x972xe2x80x9d.
Moreover, in the etching step and the doping step in the case where a LSI (Large Scale Integrated circuit) and a TFT (Thin Film Transistor) are fabricated, usually, the pretreatment for forming a protective film on a portion to which the etching treatment and the doping treatment are not performed is carried out. As for the foregoing method of forming a protective film, a method of forming it by projecting the pattern of a photomask on the substrate on which a photo resist has been coated is a type used in usual cases. Therefore, in the following explanation, the relevant protective film is defined as a xe2x80x9cmaskxe2x80x9d, and the photomask is defined as a xe2x80x9creticlexe2x80x9d. It should be noted that a mask might be formed using a material except for the photo resist. Moreover, a mask that has been formed by utilizing the photo resist being as a material is defined as a xe2x80x9cresist maskxe2x80x9d, and the mask that has been formed by utilizing the materials except for the photo resist is defined as a xe2x80x9chard maskxe2x80x9d.
The present invention fabricates the hut shape gate itself in a self-aligned process by forming a two-layer structure mask pattern as means for solving the above-described problems and by utilizing it.
The present invention is mainly configured by the mask pattern formation step and the gate formation step, hereinafter, the mask formation step and the gate formation step will be described in detail. Now, in order to discriminate the respective masks, the following definitions are provided: a mask for covering the total region of the channel formation region and the Lov region which is used in the case where a Gate Overlap LDD structure is formed is defined as a xe2x80x9cGate Overlap LDD gate maskxe2x80x9d. A mask for covering the channel region when the gate electrode on the Lov region is made thin is defined as a xe2x80x9cchannel maskxe2x80x9d. The channel mask is also used in the case where a gate for a transistor having the Loff region is formed. Moreover, in the case where a Gate Overlap LDD structure is formed, it is necessary to carry out an etching for completely removing the gate material of a portion which is not covered with the Gate Overlap LDD gate mask, and the etching for making the gate electrode on the Lov region thin by utilizing the channel mask. The former is defined as a xe2x80x9cGate Overlap LDD gate etchingxe2x80x9d, and the latter is defined as a xe2x80x9cLov region etchingxe2x80x9d.
The mask formation step is shown in FIG. 8A. An active layer 809 is formed on a substrate 808, and a gate electrode film of the first layer 811a and a gate electrode film of the second layer 811b are formed via a gate insulator film 810. Subsequently, as the preparation for a mask formation, a layer which is to be a material used for a mask is formed. Since in a usual mask formation step, a resist mask is formed only by performing the patterning, that is, only the resist is coated, however, in FIG. 8, a hard mask layer 812 is formed while it is in contact with the gate electrode film of the second layer 811b, and subsequently, a resist 813 is coated while it is in contact with the hard mask layer.
In FIG. 8B, the process for forming a resist mask 815 and a hard mask 814 is shown, that is, how the hard mask (Al) 814 is formed by performing the isotropic etching represented by a wet etching after the resist mask 815 has been formed by performing the usual patterning is shown. In FIG. 8B, the resist mask 815 which is an upper layer is formed as a Gate Overlap LDD gate mask by the usual patterning. The hard mask 814 which is a lower layer is formed as a channel mask by performing the isotropic etching represented by a wet etching utilizing a resist mask which is an upper layer. Moreover, the isotropic etching can be controlled by the setback amount of the hard mask with respect to the resist mask (amount of side etching), that is to say, the Lov can be controlled by the thickness of the hard mask layer. In the case where Lov is made large, the hard mask layer may be formed as being thick, and in the case where Lov is made small, the hard mask layer may be formed as being thin. Or, the setback amount can be controlled by making the hard mask in a certain thickness, and by controlling the over-etching time. It should be noted that in the case where it is formed by performing the wet etching, it is not necessary to consider the problems such as a corrosion, a film remaining defect and the like when the hard mask is formed.
As for a material for this hard mask, a material satisfying the two conditions of which an isotropic etching whose etching selectivity with the gate electrode is high is capable of being carried out and the etching selectivity is high in such a degree that it can be used as a mask when the Lov region is etched can be freely selected. If the side etching is essential when it is etched using the hard mask, since an air-gap is necessarily formed under the hard mask, in the later step and it can be a causing factor of the inconvenience, it is essential to remove the hard mask after the etching. However, in the present invention, as described later when the gate formation step is described, the side etching is not essential when the etching is performed using the hard mask. Therefore, in the present invention, the step of removing the hard mask after the etching is not necessarily essential. Moreover, in a process for removing the hard mask after the etching, in the case where the gate insulator film is in an uncovered condition when the hard mask is removed, the condition that xe2x80x9can etching whose etching selectivity is high with the gate insulator film is capable of being carried outxe2x80x9d should be added in relation with the hard mask material. In the present invention, since the process for making the hard mask remained without removing the hard mask is capable of being carried out, the range for selective options for the hard mask materials is widened. As a process for making the hard mask remained without removing the hard mask, for example, a process in which a silicon oxide film is selected as a hard mask material and the hard mask is made remain as a portion of the inter interlayer insulating film is listed. Moreover, in the case where as a hard mask material, a refractory metal has been selected, it is possible to make the hard mask remain as a portion of the gate electrode.
In this way, the mask pattern of the first layer (pattern of hard mask) can be formed in a self-aligned process and as a mask pattern which is analog and different in size with respect to the mask pattern of the second layer (pattern of resist mask) by performing the photolithography step only once. It is easy that the line width on the active layer is set so as to be Li in the case of the mask pattern of the first layer, and so as to be Lxe2x80x2 in the case of the mask pattern of the second layer. Although in the conventional method, the pattern of Li must be also fabricated by the resist mask, if a method according to the present invention is used, the line width of the resist mask on the active layer becomes Li+Lovxc3x972, since it can be set larger than the conventional ones, it is possible to further deal with the miniaturization.
Moreover, even if the mask pattern of the second layer which is a resist mask is peeled off, the mask pattern of the first layer which is a hard mask remains. Therefore, the anisotropic etching using the mask pattern of the second layer and the anisotropic etching using the mask pattern of the first layer can be in turn performed. Since the mask pattern of the first layer and the mask pattern of the second layer are analog and formed as mask patterns which are different in their sizes, a hut shape gate can be formed in a self-aligned process by in turn carrying out the etchings using these mask patterns. In this way, the number of reticles used in the fabricating steps is reduced, and the problems which make the fabricating method complex accompanying with the miniaturization of a TFT can be solved.
The gate formation step which is one of the main sections of the present invention will be described below. The etching using a mask having a laminated structure comprising a resist mask 916 and a hard mask 917 is carried out by dividing into 2 stages (see FIG. 9A and FIG. 9B). In FIG. 9A, how a gate electrode film of the second layer 918 is anisotropically dry-etched is shown. In FIG. 9B, how a gate electrode film of the first layer 919 is anisotropically dry-etched is shown. In the etching of the first stage, the etching of the Gate Overlap LDD gate is carried out by utilizing the resist mask 916 corresponding to the Gate Overlap LDD gate mask. It is desirable that the etching of the Gate Overlap LDD gate is carried out by performing the complete anisotropic etching. Specifically, the portions of the gate electrode film of the first layer 918 and the gate electrode film of the second layer 919 which are not covered by the Gate Overlap LDD gate mask are completely removed. As a result of this, an electrically conductive layer having the first shape 920 is formed. Subsequently, a resist mask 916 is peeled off, and the hard mask 917 is exposed (FIG. 9C).
As for an etching of the second stage, the etching (Lov region etching) which makes the gate electrode located on the Lov region into a thin film is carried out using a hard mask corresponding to the channel mask. In FIG. 10A, how only a gate electrode film of the second layer 1024 is anisotropically dry-etched by utilizing a hard mask 1023 as a mask is shown. Subsequently, the hard mask 1023 is removed by carrying out the isotropic etching represented by a wet etching (see FIG. 10B). As described above up to this point, an electrically conductive layer 1026 having the second shape which is a hut shape gate is formed in a self-aligned process. Subsequently, the impurity is added to the source and drain regions in a high concentration, and the impurity is added to the Lov region in a low concentration.
In this way, a mask having a structure in which a resist mask is laminated on the hard mask referred to as a major part of the present invention is utilized, in the case of a hard mask, it is set so as to be Li, and in the case of a resist mask, it is set so as to be Lxe2x80x2, and a hut shape gate can be formed in a self-aligned process by in turn carrying out the anisotropic etching using a resist mask and the anisotropic etching using a hard mask. Therefore, the number of reticles used in the fabricating steps is reduced and the problems which make the fabricating method complex accompanying with the miniaturization of a TFT can be solved.
In the explanation described above, the electrically conductive film which is to be a gate electrode has been a two-layer structure composed of different materials. Owing to this, it is possible that the electrically conductive layer of the first layer (lower layer) is made an etching stopper when the electrically conductive layer of the second layer (upper layer) is etched. In this way, the range of the selective options of the conditions in which the electrically conductive film which is to be a gate electrode is etched can be enlarged. The effect is large particularly when the Lov region is etched, and it can make the gate film thickness precisely controlled and as a result of this, the concentration of the impurities which is added to the Lov region in the later step can be easily controlled.
Moreover, if the present invention is applied, a pretty large number of combinations of the first electrically conductive film and the second electrically conductive film which configure a hut shape gate can be selected, and the second electrically conductive film is not limited to an aluminum film. The above-described first and second electrically conductive films may be formed with an element selected from Ta (tantalum), W (tungsten), Ti (titanium), Mo (molybdenum), Al (aluminum), and Cu (copper) or an alloy material or compound whose main component is the foregoing element. Moreover, a semiconductor represented by a polycrystalline silicon film to which an impurity element such as phosphorus or the like has been doped may be used. Moreover, the combination of the first electrically conductive film being formed with a tantalum (Ta) film and the second electrically conductive film being made with tungsten (W) may be used, and the combination of the first electrically conductive film being formed with tantalum nitride (TaN) film and the second electrically conductive film being made with copper (Cu) film may be used. Since a refractory metal can be selected as a gate material, the activation of an impurity can be carried out by a usual thermal treatment (550-800xc2x0 C.).
However, it is not an essential condition that the gate electrode film is configured with two layers. If the etching of the Lov region is precisely controlled, it is also possible to configure the gate electrode film with a single layer film. Even if the gate electrode film is configured with a single layer film, a hut shape gate is capable of being formed by the application of the present invention.
Moreover, as the typical values, Li=1.0-2.0 xcexcm, and Lov=0.25-0.5 xcexcm are listed. However, these values are not necessarily limited to these ranges.
According to a fabricating method of the present invention, a mask (hard mask) of the first layer can be formed in a self-aligned process and as a mask pattern which is analog, but which is different in size with respect to a mask of the second layer (resist mask) by carrying out the photolithography step only once. A TFT having only the Loff region can be formed in a self-aligned process by setting the line width on the activation layer so as to be Li in the mask patter of the first layer and so as to be Li+Loffxc3x972 in the mask pattern of the second layer, and by in turn carrying out the anisotropic etching using the mask pattern of the second layer and the anisotropic etching using the mask pattern of the first layer. Therefore, the number of reticles used in the fabricating step is reduced, and the problem of the complexity of the fabricating method accompanying with the miniaturization of a TFT can be solved. Moreover, since a single-layer electrically conductive film or a laminated electrically conductive film, which is to be a material for the gate electrode can be optionally selected from the large number of materials without being limited to aluminum, the activation of an impurity can be carried out by a usual thermal treatment (550-800xc2x0 C.).
Moreover, as the typical values, Li=1.0-2.0 xcexcm, and Loff=0.25-0.5 xcexcm are listed. However, these values are not limited to these ranges. Owing to these, even if it is a process for fabricating a TFT having only the Loff region whose miniaturization has been progressed, the line width of the resist mask located on the active layer is not miniaturized, but the patterning margin can be enlarged.
Moreover, the hard mask may be formed by a wet etching treatment using a resist mask. Owing to this, in a process of fabricating a TFT having only the Loff region whose miniaturization has been progressed, the problems such as the dispersion of the film thickness and the occurrences of the irregularity of etching, corrosion, the film remaining defect and the like can be prevented.
It should be noted that a p-channel type TFT might be made a Gate Overlap LDD structure, or a n-channel type TFT might be made a Gate Overlap LDD structure. Moreover, both of them may be made a Gate Overlap LDD structure.